Ben Cohen’s Post

Books vs Internet/AI: Which to pick and why? In todays' technology, would you buy a book or use Google searches with AI to learn a technology (e.g., SV, SVA, UVM, C++, Design, manufacturing, etc). Is book technology dead? Would love to hear your comments, the more the better. You can be brief in your response if you wish, but more replies would be more meaningful.

SVA: 1800’2023 Degeneracy Issue to Hopefully be Addressed in 1800’2028 When faced with degenerate sequences, 1800’2023 is unclear on what a simulator should do, particularly in situations resulting from parameter substitution that creates a degenerate sequence. In that situation, it would be undesirable to have to rewrite the code to get to a successful compilation. Existing tools differ in their interpretation of degenerate sequences - some report it as a degenerate situation, some issue a warning, and some proceed with the simulation. This linked document identifies the sections in the LRM that define degeneracy and highlights cases that pose challenges for users and tool vendors. Additionally, it proposes solutions for the next revision of the LRM. Ben, in collaboration with Ed Cerny https://lnkd.in/gsvUBKav

Verification: A verification chip designer walks into a bar and orders a drink. As he sits there, he starts talking to the bartender about his work. "You wouldn't believe it," he says, "but I'm training an AI to help me verify my chip designs. It's incredible! It can catch bugs I would have missed for hours." The bartender leans in, intrigued. "That's amazing! So, what kind of bugs does it find?" The engineer smiles proudly. "Oh, the usual suspects. Logic errors, timing issues, memory leaks... you name it!" The bartender nods. "Sounds impressive. But what about the really tricky ones? The ones that take a seasoned engineer to spot?" The engineer takes a sip of his drink and winks. "Those? Well, that's why I still have a job. The AI can only find bugs it understands."

SVA: $rose(seq.triggered)[->1]; // OK ?? NO! The endpoint status of of .triggered is set in the Observed region. It persists until the end of the timestep. Also, always_ff @(posedge clk) if(seq.triggered) a <= b; // BAD USE • Triggered may be used in wait statements • 1800 seem to imply that .triggered cannot be used with the “@” construct, like @(seq.triggered). Tools do not agree in the compilation of the triggered with the “@”. Many experts believe that this is illegal. Avoid using such a construct. Use the wait instead. The matched status of the sequence is set in the Observed region and persists until the Observed region following the arrival of the first clock tick of the destination sequence after the match. https://lnkd.in/g9-YPWzN

SVA: Check sig after an async reset From: https://lnkd.in/gSYwZWG2 Options I see:   always@(negedge reset) am_reset_sig: assert final(sig==0);  always_comb    if($fell(reset, @(posedge clk))) am2_reset_sig: assert final(sig==0);

If you read my SVA book would you be willing to write an honest review on Amazon? Thanks, Ben SystemVerilog Assertions Handbook Revised 4 th edition 2023: … for Dynamic and Formal   https://lnkd.in/gESFqFFm  

4SVA: Assertion example from my PSL book. Although I do not recommend PSL, I am contributing a chapter from my PSL book (before SVA) that demonstrates how assertions can be used to clarify requirements and verification processes. This chapter showcases a design that includes an AMBA™ AHB bus and an IDT 71V433 Synchronous pipelined SRAM2. The chapter (and code) also includes simulation results of the model using a PSL-aware simulator for verification. My goal here is to demonstrate assertion approaches and their values in the clarification of the requirements, design and verification processes. Though written in PSL, the assertions can easily be converted into SVA; SVA was derived from PSL. https://lnkd.in/gyPT33ab

SVA: Local variables passed to task/function should NOT be passed by reference. Reasons: 1) Bad style 2) May not get desired value because of misinterpretations by tools. Example: task automatic sub1( int ip1 , ref int ip2 );         $display("ip1 == %0d",ip1); // OK   $display("ip2 == %0d",ip2); // BAD STYLE   $display("a == %0d\n",a); // "a" value in the Observed Region  endtask     property p;    @(posedge clk) (1,sub1(a,a));   endproperty Code: https://lnkd.in/gCdUsrpU https://lnkd.in/gy_tVH-U 1800'2023 13.5.2 Pass by reference  Arguments passed by reference are not copied into the subroutine area,  rather, a reference to the original argument is passed to the subroutine.   ...  When the argument is passed by reference, both the caller and the subroutine  share the same representation of the argument; therefore, any changes made to the argument,  within either the caller or the subroutine, shall be visible to each other.  The semantics of assignments to variables passed by reference is  that changes are seen outside the subroutine immediately (before the subroutine returns).